1. Field of the Invention
This invention relates to a compiler, circuits and a method for generating a flash memory for integrated circuits.
More particularly this invention relates to providing a flash memory compiler which can generate flexible configurations which are a function of the flash memory array bit count. In addition, this invention relates to the ability of a flash compiler to optimize the resultant flash memories so as to produce the correct amount of flash array current driving capability and minimal wasting of power dissipation.
2. Description of Related Art
FIG. 1 shows a prior art charge pumping circuit. There are thirteen stages of an identical charge pumping circuit macro 120. Each stage 120 has an input 110 and an output 125. The output 125 of one stage 120 feeds the input of the next stage 130. The logical input to the first stage is the Enable signal 110. This signal starts the charge pumping process. The output of the thirteenth and final stage 140 is the High Voltage signal, HV 150. The significant feature of the charge pumping circuit of FIG. 1 is that each stage contains the same pumping circuit with identical capacitance independent of flash array bit count or IO count.
U.S. Pat. No. 5,568,424 (Cernea, et al.) “Programmable Power Generation Circuit for Flash EEPROM Memory Systems” describes a voltage and power circuit to drive a variety of flash memory systems. These flash memories include those on the same chip and those off-chip.
U.S. Pat. No. 5,693,570 (Cernea, et al.) “Process for Manufacturing a Programmable Power Generation Circuit for Flash EEPROM Memory Systems” describes a process for making a variety of voltage and power generating circuits for various sizes and types of flash memories.
U.S. Pat. No. 5,693,570 (Cernea et al.) “Programmable Power Generation Circuit for Flash EEPROM Memory Systems” discloses a circuit for on-chip generation of voltage and power for flash memories.